Selected Publications – David Hutchinson |
Publications in
Refereed Journals
1.
J. S. Vitter and D. A.
Hutchinson, “Distribution Sort with Randomized Cycling”, Journal of the ACM, Volume 53, Issue 4,
pp. 656-680, 2006. [.pdf] [abstract]
2.
D. A. Hutchinson, P. Sanders, and J. S. Vitter.
“Duality Between Prefetching and Queued Writing with Parallel
Disks”, SIAM Journal on Computing, 34(6), 1443-1463, June
2005. [.pdf] [abstract]
3.
D. Hutchinson, A. Maheshwari, and N. Zeh. "An External
Memory Data Structure for Shortest Path Queries", Discrete Applied
Mathematics, 126(1):55–82, 2003 (special issue on the 5th
ACM-SIAM COCOON conference). [.pdf]
4.
F. Dehne, W. Dittrich, D. Hutchinson, "Efficient external
memory algorithms by simulating coarse-grained parallel algorithms", Algorithmica, Vol. 36, 2003, pp. 97-122. [.pdf]
[abstract]
5.
F. Dehne, W. Dittrich, D. Hutchinson, A. Maheshwari,
“Bulk synchronous parallel algorithms for the external memory
model”, Theory of Computing Systems, Vol. 35 Issue 6, 2002, pp.
567-598. [.pdf] [abstract]
6.
W. Dittrich, D. Hutchinson and A. Maheshwari, “Blocking in Parallel Multisearch Problems”, Theory of Computing Systems, 34(2):
145-189, 2001 (invited papers from the 1998 ACM-SPAA conference). [.pdf] [abstract]
Publications
in Refereed Conferences
1.
M. Nikseresht, D. Hutchinson and A. Maheshwari, "Experiments With A Parallel
External Memory System",
14th Annual IEEE International Conference on High Performance Computing (HiPC), Goa, India, December 2007. [.pdf]
[abstract]
2.
D. A. Hutchinson, P. Sanders, and
J. S. Vitter. "Duality between Prefetching and Queued Writing with
Parallel Disks", In Proceedings of the 9th Annual European Symposium on
Algorithms (
3.
D. A. Hutchinson, P. Sanders, and J. S. Vitter. “The
Power of Duality for Prefetching and Sorting with Parallel Disks”, in Proc.
of the 13th Annual ACM Symposium on Parallel Algorithms and
Architectures (SPAA '01), Crete, Greece, July 2001. [.pdf][abstract]
4.
J.
S. Vitter and D. A. Hutchinson. “Distribution Sort with Randomized
Cycling”, in Proc. of the 12th Annual SIAM/ACM Symposium on
Discrete Algorithms (SODA '01), Washington, DC,
January 2001. [.pdf][abstract]
5.
D. Hutchinson, A.
Maheshwari, and N. Zeh, “An External Memory Data Structure for Shortest
Path Queries”, in Proceedings of
the 5th Annual International Computing and Combinatorics Conference
(COCOON'99), Tokyo, Japan, July 26-28, 1999, pp. 51-60. [.pdf][abstract]
6.
F. Dehne, W. Dittrich,
D. Hutchinson, and A. Maheshwari, “Reducing I/O Complexity by Simulating
Coarse Grained Parallel Algorithms”, in Proc. 13th International Parallel Processing Symposium
(IPPS'99), San Juan, Puerto Rico, April 1999, pp. 14-20. [.pdf][abstract]
7.
F. Dehne, W. Dittrich,
D. Hutchinson, and A. Maheshwari, “Parallel Virtual Memory”, in Proc. of the Tenth Annual ACM-SIAM
Symposium on Discrete Algorithms (SODA'99), Baltimore, Maryland
January 1999, pp. 889-890. [.pdf][abstract]
8.
W. Dittrich, D.
Hutchinson, and A. Maheshwari, “Blocking in Parallel Multisearch
Problems”, Proc. of the 10th Annual
Symposium on Parallel Algorithms and Architectures (SPAA'98), Puerto
Vallarta, Mexico, June 1998, pp. 98-107.
[.pdf][abstract]
9.
D. Hutchinson, A.
Maheshwari, J.-R. Sack, and R. Velicescu, “Early Experiences in
Implementing the Buffer Tree”, Workshop
on Algorithmic Engineering (WAE'97), Venice, Italy, September 1997. [.pdf][abstract]
10.
F. Dehne, W. Dittrich,
and D. Hutchinson, “Efficient External Memory Algorithms by Simulating
Coarse-Grained Parallel Algorithms”,
Proc. 9th Annual Symposium on Parallel Algorithms and Architectures
(SPAA'97), Newport R.I., USA, June 1997. [.pdf][abstract]
11.
D. Hutchinson, M.
Lanthier, A. Maheshwari, D. Nussbaum, D. Roytenberg, and J.-R.Sack,
“Parallel Neighbourhood Modelling”, Proceedings of the Fourth ACM Workshop on Advances in Geographic
Information Systems, Rockville MA, USA, Nov. 1996, pp.25-34. [.pdf][abstract]
12.
D. Hutchinson, L.
Kuttner, M. Lanthier, A. Maheshwari, D. Nussbaum, D. Roytenberg, and J.-R.
Sack, “Parallel Neighbourhood Modeling: Research Summary”, Proc. of the 8th Annual Symposium
on Parallel Algorithms and Architectures (SPAA '96), Padua, Italy, June
1996, pp. 204-207. [.pdf][abstract]
Ph.D.
Thesis
1.
D. Hutchinson,
“Parallel Algorithms in External Memory”, PhD Thesis, School of
Computer Science, Carleton University, May 1999. Advisors: F. Dehne, A.
Maheshwari, J.-R. Sack. External Examiner: A. Ranade. [.pdf][abstract]
Other
Publications