Table of Contents

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• Introduction
• An emulator of the ATARI processor
• Download the Software
• Documentation
• Tests
• Publications related with the project

As part of this project, a group of students developed a emulator of the ATARI processor . This work obtained the 1st. prize in the 1999 undergraduate student contest in the Argentine Meeting on Informatics (JAIIO) .

The tool was tested exhaustively, and few bugs have been reported (mainly, the UDIV instruction is not working properly). The bugs were fixed.

To execute the simulated computer you should download the CD++ toolkit and the model corresponding to the simulated computer.
• [ Download the CD++ tool ] Simulation Software
• [ Download the simulated computer ] Models defining the architecture
• [ Download an extended version of the simulated computer ] including new components

This section includes several documents (most in Spanish) explaining the model definition, tests, and some execution results obtained. The documents in English include the [E] notice (many of the documents are understandable, even they are written in Spanish).


• [ User manual ] This document explains how to install the tool and run the simulated processor.
• [ Technical description [E]. ] Here we include a detailed of the processor's architecture, how to use it, how to make changes, and some experiences. It includes parts of other documents, reorganized to understand the complete experience.
• [ Architectural description. ] Here we include the description of the processor's architecture used to build the simulated models.
• [ Control Unit description. ] The description of the Control Unit behavior is useful to understand how the instruction flow is carried out.
• [ Architecture Description [E]. ] The architecture is briefly described in English
• [ Assembly Language Instruction Set. ] Here we include a brief description of the assembly language for the SPARC cpu.
• [ Component description. ] This document includes the description of some of the components used to built the simulated computer
• [ Component description II. ] Here we describe another set of models included in the computer.
• [ Exhaustive tests ] We describe the seet of integration tests carried out by executing simple programs which activate different instructions.

The simulated computer was tested thoroughly. The computer can run executable code for the SPARC processor, that can be generated using the GNU Assembly Language for the SPARC .

You can see a set of exhaustive tests in in this file . The archive includes different types of files. Those with ".s" extension represent SPARC assembly language source code. The ".map" files represent the memory map representing the executable file. The ".tst" files include external values that are fed into the simulator to be tested (representing memory variables and their value contents).

This file includes an extended version of the tests, including the log files corresponding to the execution of the tests.

The following document (in Spanish) describes the set of tests applied to the simulated computer. Each one of the tests here described are included in the source files previously mentioned.

Finally, the following files include the log files corresponding to the execution for each of the tests.

YOU CAN OBTAIN COPIES OF THESE PUBLICATIONS CLICKING HERE


• "Experiences in modelling and simulation of computer architectures using DEVS". S. Daicz; A. Troccoli, G. Wainer. Accepted to be published in Transactions of the Society for Computer Simulation.
  
  
• "Using the DEVS paradigm to implement a simulated processor". Alejandro Tróccoli, Gabriel Wainer, Sergio Zlotnik. In Proceedings of the 33rd Anual Conference on Computer Simulation. Washington, D.C. U.S.A.
  
  
• "ALFA-0: a simulated computer as an educational tool for Computer Organization". G. Wainer. In Proceedings of IASTED Applied Modelling and Simulation 1998. Hawaii, USA