[ Back to homepage | Back to Information ]

ALFA-1    Information

Top ]

The theoretical study of computer architecture and organization usually give the students an incomplete and sometime erroneous view of how a computer system works. The lack of practical experience can make that the underlying complexity of the subsystems and their interaction could not be completely understood. The goal of this project is to provide tools based on computer simulation to allow the students to experience with computer architecture. A formal approach is used, improving the development process, the maintanability and the chance to change architectural components.

A set of tools of isolated tools devoted to simulate the components of a computer were developed. These tools have the problem of an increased complexity when making intermodule interconnection, and detailed implementation. To avoid these problems, the simulated computer was completely redesigned. In this case, a formal approach was taken into account. The DEVS formalism was used, due to the discrete event characteristics of the system to be modeled, and the hierarchical nature of the problem.

The tool GAD was built to implement the theoretical concepts of the DEVS formalism. It was built using a C++, and a modeling class hierarchy was defined. Atomic models should be programmed and incorporated to the class hierarchy. A specification language allows to define the model coupling, initial values and external events. This tool was used as a basis to develop the simulated computer, allowing to experiment with the formal approach defined by the DEVS formalism. This tool is running under different environments (using the GNU C++ compiler under Solaris, AIX, Linux, Windows and SunOs; at present is being ported to run in an Sillicon Graphics multiprocessor using Irix). Hence, all the models developed in any plattaform can be directly reused, including, in this case, the models defining the simulated computer.

At present, the implementation of several components of the simulated computer is almost finished. Every component has been built as a DEVS model, and they are being tested thoroughly. The Control Unit definition is being finished, and it is being implemented. The final product will be a complete simulated computer so as the students can experience the construction of a whole computer, to analyze performance improvements, and to develop basic software from scratch.

[ Back to homepage | Back to Information | Back to top ]
[ Staff | Introduction | Simulation Project | Simulation Mailing List | Links ]

[ Information | Goals | Courses | Results ]

Comments: Gabriel A. Wainer - Webmaster: Sebastian Enrique
Last Update: June 26, 2000