Saied Hemati, Ph.D., SMIEEE

Email: saied.hemati (at) gmail.com

Research Interests

· Channel coding applications and iterative decoding algorithms

· Low-power/high-speed analog/digital integrated circuits for communication systems

· Applications of information theory in nanoelectronics

· Low-power/reliable system design using leaky/non-deterministic components

· Ultra low-power weakly inverted (subthreshold) MOSFET circuit design for health monitoring devices and sensor networks

Awards & Honors

· ReSMiQ (Le Regroupement Stratégique en Microsystèmes du Québec) Postdoctoral Fellowship, September 2009 ($20,000).

· Promoted to IEEE Senior Member, March 2008.

· Canadian Space Agency NSERC Postdoctoral Fellowship Supplement Award, April 2006 ($26,666).

· Senate Medal for Outstanding Academic Achievements, November 2005.

· NSERC Postdoctoral Fellowship (NSERC PDF), March 2005 ($80,000).

· Ontario Graduate Scholarship (OGS), April 2004 ($15,000).

· Ontario Graduate Scholarship in Science and Technology (OGSST), September 2003 ($10,000).

· CITO Research Excellence Scholarship, May 2003 ($5,000).

· Best Paper Award, 2002 CITO Knowledge Network Conference, Ottawa, Canada, Oct. 2002 ($500).

· CITO Graduate Scholarship, 2002 ($2,000).

· Carleton University Graduate Scholarship, 2001-2005.

· Integrated Electronics Industry Golden Medal Paper Award, 1998.

Books

· S. Hemati, Iterative Decoding in Analog VLSI, Dynamics and Circuits, VDM, ISBN: 978-3-639-17539-4, 2009.

Issued Patents

· S. Hemati and A. H. Banihashemi, “Full CMOS Min-Sum Analog Iterative Decoders” US Patent No: 7,769,798; issued on August 3, 2010.

Publications

Refereed Journal Papers:

11- K. Cushon, C. Leroux, S. Hemati, S. Mannor, and W. Gross, “A Min-Sum Iterative Decoder with Pulse Width Message Encoding,” IEEE Trans. Circuits and Systems-II, vol. 58, no. 11, pp. 893-897, November 2010.

10- C. Leroux, S. Hemati, S. Mannor, and W. Gross, “Stochastic Chase Decoding of Reed-Solomon Codes,” IEEE Communications Letters, vol. 14, no. 9, pp. 863-865, September 2010.

9- S. Sharifi Tehrani, A. Naderi, G.-A. Kamendje, S. Hemati, S. Mannor, and W. J. Gross “Majority-Based Tracking Forecast Memories for Stochastic LDPC Decoding,” IEEE Transactions on Signal Processing, vol. 58, no. 9, pp. 4883-4896, September 2010.

8- S. Hemati and A. Yongacoglu, “On the Dynamics of Analog Min-Sum Iterative Decoders, an Analytical Approach,” IEEE Transactions on Communications, vol. 58, no. 8, August 2010.

7- S. Hemati and A. Yongacoglu, “Dynamics of Analog Decoders for Different Message Representation Domains,” IEEE Transactions on Communications, vol. 58, no. 3, pp. 721-723, March 2010.

6- N. Mobini, A. H. Banihashemi, and S. Hemati, “A Differential Binary Message-Passing LDPC Decoder,” IEEE Transactions on Communications, vol. 57, no. 9, pp. 2518-2523, September 2009.

5- S. Hemati and A. H. Banihashemi, “Convergence Speed and Throughput of Analog Decoders,” IEEE Transactions on Communications, vol. 55, no.5, pp. 833-836, May 2007.

4- S. Hemati, A. H. Banihashemi, and C. Plett, “A 0.18mm Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code,” IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2531-2540, Nov. 2006.

3- S. Hemati and A. H. Banihashemi, “Dynamics and Performance Analysis of Analog Iterative Decoding for Low-Density Parity-Check (LDPC) Codes,” IEEE Transactions on Communications, vol. 54, no.1, pp. 61-70, Jan. 2006.

2- M. R. Yazdani, S. Hemati, and A. H. Banihashemi, “Improving Belief Propagation on Graphs with Cycles,” IEEE Communications Letters, vol. 8, no. 1, pp.57-59, Jan. 2004.

1- S. Feiz and S. Hemati, “Dispersion Evaluation in Optical Waveguides,” ESTEGHLAL, J. of Engineering, vol. 18, no.1, pp. 23-31, 1999.

Refereed Conference Papers:

42- F. Leduc-Primeau, S. Hemati, W. Gross, and S. Mannor, “Lowering Error Floors Using Dithered Belief Propagation,” to appear in Proceedings of the IEEE Globecom 2010 Communication Theory Symposium, Miami, FL, USA.

41- G. Sarkis, S. Hemati, W. Gross, and S. Mannor, “Relaxed Half-Stochastic Decoding of LDPC Codes over GF(q),” in Proceedings of Annual Allerton Conference on Communication, Control and Computing , University of Illinois, 2010.

40- F. Leduc-Primeau, S. Hemati, W. Gross, and S. Mannor, “A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes,” in Proceedings of IEEE Globecom 2009 Communication Theory Symposium, pp. 1-6, Nov. 2009, Honolulu, Hawaii, USA.

39- S. Hemati and A. Yongacoglu, “On the Dynamics of Analog Min-Sum Iterative Decoders, an Analytical Approach,” in Proceedings of CWIT 2009, Ottawa, Canada, pp. 29-31, May 13-15, 2009.

38- S. Hemati and A. Yongacoglu, “Effects of Message Representation Domain on the Dynamics of Analog Decoders,” in Proceedings of the 2008 Analog Decoding Workshop, Utah, US, July 2008.

37- N. Mobini, A. H. Banihashemi, and S. Hemati, “A Differential Binary Message-Passing LDPC Decoder,” in Proceedings of the IEEE Globecom 2007 Communication Theory Symposium, Washington, DC, US, pp. 1561-1565, Nov. 2007.

36- S. Hemati and A. Yongacoglu, “On the Dynamics of Analog Min-Sum Iterative Decoders, an Analytical Approach,” in Proceedings of the 2007 IEEE International Symposium on Information Theory, ISIT2007, Nice, France, June, 2007.

35- S. Hemati and A. Yongacoglu, “Stability and Singularity in Analog Min-Sum Decoders,” in Proceedings of the 6^th Analog Decoding Workshop, Montreal, Canada, May 2007.

34- N. Mobini, A. H. Banihashemi, and S. Hemati, “Differential Decoding of LDPC Codes with Binary Message-Passing,” in Proceedings of the 6^th Analog Decoding Workshop, Montreal, Canada, May 2007.

33- S. Hemati and A. Yongacoglu, “On the Solvability of the Dynamic Equations for Analog Min-Sum Decoders,” in Proceedings of the 5^th Analog Decoding Workshop, Turin, Italy, pp.47-50, June 2006.

32- S. Hemati and A. H. Banihashemi, “Convergence Speed and Throughput of Analog Iterative Decoders for Low-Density Parity-Check (LDPC) Codes,” in Proceedings of the 4^th International Symposium on Turbo Codes, Munich, Germany, April 3 - 7, 2006.

31- S. Hemati and A. H. Banihashemi, “A Low-Voltage 4-Input CMOS Analog Maximum Winner-Take-All Chip for Min-Sum Analog Iterative Decoders,” The CMC Microsystems 2006 Annual Symposium, Ottawa, October 2006.

30- S. Hemati and A. H. Banihashemi, “Convergence Speed and Throughput of Analog Decoders,” in Proceedings of CWIT 2005, Montreal, Quebec, Canada, pp. 235-238, June 5 - 8, 2005.

29- S. Hemati, A. H. Banihashemi, and C. Plett, “An 80-Mb/s 0.18-mm CMOS Analog Min-Sum Iterative Decoder for a (32,8,10) LDPC Code,” in Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Jose, California, pp. 240-243, Sept. 18 -21, 2005.

28- S. Hemati, A. H. Banihashemi, and C. Plett, “A High-Speed Analog Min-Sum Iterative Decoder,” in Proceedings of the IEEE International Symposium on Information Theory, ISIT 2005, Adelaide, Australia, pp. 1768-1772, Sept. 4 - 9, 2005.

27- S. Hemati, A. H. Banihashemi, and C. Plett, and N. Ogbebor “An Analog Min-Sum Decoder for a (32,8) LDPC Code,” in Proceedings of CWIT 2005, Montreal, Quebec, Canada, pp. 203-206, June 5 - 8, 2005.

26- S. Hemati and A. H. Banihashemi, “A Novel CMOS Analog Min-Sum Iterative Decoder,” Microsystems Research and Development in Canada 2004, Ottawa, Canada, Sept. 2004.

25- S. Hemati and A.H. Banihashemi, “Comparison between Continuous-Time Asynchronous and Discrete-Time Synchronous Iterative Decoding,” in Proceedings of the IEEE Globecom 2004, Dallas, Texas, USA, pp.356-360, Nov. 29 - Dec. 3, 2004.

24- S. Hemati and A.H. Banihashemi, “On the Dynamics of Continuous-Time Analog Iterative Decoders,” in Proceedings of the 2004 IEEE International Symposium on Information Theory, ISIT2004, Chicago, US, p. 262, June 27-July 2, 2004.

23- S. Hemati and A. H. Banihashemi, “A Current-Mode Maximum Winner-Take-All Circuit with Low Voltage Requirement for Min-Sum Analog Iterative Decoders,” in Proceedings of the 10^th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003, Sharjah, UAE, pp. 5-7, December 14 -17, 2003.

22- S. Hemati and A. H. Banihashemi, “Novel Circuits for Implementing High-Degree Parity-Check and Variable Nodes in Full CMOS Analog Min-Sum Iterative Decoders,” 2^nd Analog Decoding Workshop Zürich, Switzerland, September 2003.

21- S. Hemati and A. H. Banihashemi, “Full CMOS Min-Sum Analog Iterative Decoder,” in Proceedings of the 2003 IEEE International Symposium on Information Theory, ISIT2003, Yokohama, Japan , p. 347, June 29-July 4, 2003.

20- S. Hemati and A. H. Banihashemi, “Iterative Decoding in Analog CMOS,” in Proceedings of the 13^th ACM Great Lakes Symposium on VLSI, ACM GLSVLSI 2003, Washington D.C., USA, pp. 15-20, April 27-29, 2003.

19- S. Hemati and A. H. Banihashemi, “On the Dynamics of Analog Asynchronous Iterative Decoders,” in Proceedings of the 41^st Annual Allerton Conference on Communication, Control and Computing , University of Illinois, US, pp.1679-1687, October 1-3, 2003.

18- S. Hemati and A. H. Banihashemi, “Analog Asynchronous Iterative Decoding, Different Dynamics with Better Performance,” 2^nd Analog Decoding Workshop Zürich, Switzerland, September 2003.

17- M. R. Yazdani, S. Hemati, and A. H. Banihashemi, “Improving Belief Propagation on Graphs with Cycles,” in Proceedings of the 2003 Canadian Conference on Information Theory, CWIT2003, Waterloo, Ontario, Canada, pp.235-238, May 18-21, 2003.

16- S. Hemati and M. Emadi, “A Method for Analyzing Higher-Order Dispersion in Optical Fiber,” in Proceedings of the 2003 IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2003, Montreal, Canada, pp.289-292, May 4 -7, 2003.

15- F. Farahmand and S. Hemati, “An Algorithm Based on Evolutionary Programming for Training Artificial Neural Networks with Non-Conventional Neurons,” in Proceedings of the 2003 IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2003, Montreal, Canada, pp.1845-1848, May 4 -7, 2003.

14- A. H. Banihashemi and S. Hemati, “Decoding in Optics,” in Proceedings of the 2002 IEEE International Symposium on Information Theory, ISIT 2002, Lausanne, Switzerland, p.231, June 30-July 5, 2002.

13- S. Hemati and A. H. Banihashemi, “Low-Cost High-Performance Analog Iterative Decoders,” 2002 Cito Knowledge Network Conference, Ottawa, Canada, Oct. 2002. Won the best paper award

12- S. Hemati and A. H. Banihashemi, “New Analog VLSI Circuits for Iterative Decoding,” in Proceedings of the 21^st Biennial Symposium on Communications, Queen's University, Kingston, Ontario, Canada, pp. 261-263, June 2-5, 2002.

11- A. H. Banihashemi and S. Hemati, “ Electro-optical Implementation of Iterative Decoding Algorithms,” in Proceedings of the 21^st Biennial Symposium on Communications, Queen's University, Kingston, Ontario, Canada., pp. 474-475, June 2-5, 2002.

10- S. Hemati and A. H. Banihashemi, “Advanced Coding Schemes in Modern WDM Networks,” 2002 Cito Knowledge Network Conference, Ottawa, Canada, Oct. 2002.

9- S. Hemati and A. H. Banihashemi, “Towards Photonic Decoders,” in Technical digest of the Eighth Microptics Conference, MOC’01, Osaka, Japan, pp.218-221, October 2001.

8- S. Hemati,“ WDM Optical Components”, Eighth Iranian Conference on Electrical Engineering,ICEE2000, Isfahan University of Technology, Isfahan, Iran, May 2000.

7- A. Adibi, V. Tahani, S. Hemati, and F. Farahmand, “ Neural Networks with Non-Conventional Synapses,” in Proceedings of the Eighth Iranian Conference on Electrical Engineering, ICEE2000, Isfahan, Iran, pp.68-75, May 2000.

6- A. Adibi and S. Hemati, “A Novel Implementation of the Hebbian Neurons by Subthreshold MOSFETs in the Presence of Mobile Ions, ” in Proceedings of the Seventh Iranian Conference on Electrical Engineering, ICEE99, Iran Telecommunication Research Center, Tehran, Iran, pp. 41-48, May 1999.

5- S. Feiz and S. Hemati, “ Precise Formula for Zero Material Dispersion Analysis of the Optical Fiber Core,” in Proceedings of the International Conference on Communication, Computer & Power, ICCCP98, Sultan Qaboos University, Muscat, Sultanate of Oman, pp. 19-23, December 1998.

4- S. Feiz and S. Hemati, “Dispersion Evaluation by Monte Carlo Simulation,” in Proceedings of the Fifth Iranian Physics Conference, Optics Session, Iran University of Science and Technology, Tehran, Iran, pp. 11-14, June 1998.

3- S. Feiz, S. Hemati, and M. Bahadoran,“ Evaluation of Material Dispersion in Optical Fibers According to Instantaneous Spectrum of the Light Source,” in Proceedings of the sixth Iranian Conference on Electrical Engineering, ICEE98, K.N. Toosi University of Technology, Tehran, Iran, pp. 79-84, May 1998.

2- S. Feiz, S. Hemati, and M. Emadi, “ Exact Determination of Material Dispersion in SI Optical Fibers,” in Proceedings of the Fifth Iranian Conference on Electrical Engineering, ICEE97, Sharif University of Technology, Tehran, Iran, pp. 24-31, May 1997.

1- S. Feiz and S. Hemati, “ Exact Determination of the Derivatives of the Refractive Index of the Optical Fiber Core,” in Proceedings of the Fourth Iranian Conference on Electrical Engineering, ICEE96, University of Tehran, Tehran, Iran, pp. 225-228, May 1996.

Technical Skills

· Expert knowledge in analog and mixed-signal MOSFET/ Bipolar circuit design (Winner-take-all circuits, current-mode design, low voltage circuits, current mirrors and current mode design, operational amplifiers, DA or AD converters, amplifiers, voltage regulators and band gap voltage reference, …).

· Experience in all aspects of analog chip design including definition, schematic entry, layout design and trade-offs, simulations, designing experiments, designing test benchmark, silicon validation, and debug.

· Proficiency in solid state physics, VLSI design, and VLSI fabrication.

· Proficiency in extremely low-power design and weakly inverted (sub-threshold) MOSFET design.

· Experience in RF IC design (LNA, oscillator, mixer, and power amplifier) for GSM cell phones.

· Proficiency with the following CAD tools: Spectre/ SpectreRF / HSpice simulators, Cadence design framework, Matlab, Simulink, HP ADS simulation tools, Virtuoso Layout Editor, DIVA / Assura / Calibre Verification tools.

· Excellent mathematical and statistical skills and strong problem-solving skills.

· Experience in teaching and mentoring graduate students in all aspects of chip design.

· Enjoy working on interdisciplinary fields, prior experience with digital communications and coding theory, neural networks, and optical communications. Willing to learn and acquire knowledge and new experiences.