Thesis Topics - Professor T. Pearce
Room 3038 Minto CASE, phone 520-2600 ext 4054
Email:  Trevor.Pearce@sce.carleton.ca
URL: http://www.sce.carleton.ca/faculty/pearce.html

Professor Pearce is on sabbatical from July 1, 2001 to June 30, 2002
He will be answering email during this period.

Professor Pearce is an active member of the Embedded Systems Group. Current interests in this area are in real-time systems, with an interest in simulation based on the High Level Architecture (HLA).

No./Title:         Pearce - 1     Integrating Timing Diagram Protocols with HLA Simulations
Level:              Master's
Background:   embedded systems, discrete event simulation

Synopsis: Hardware components interact using bus protocols. These protocols are usually expressed using timing diagrams that relate signal transitions to component responsibilities and progress through interactions. Designers work with the visual timing diagrams. For HLA-compatible simulations of components, the information associated with the timing diagrams must be converted into simulation events and changes to state variable values.

This research involves the design of an HLA-compatible framework for incorporating bus protocols with hardware component simulations, the construction of a tool to support the framework, and demonstrating the tool on case studies.

The framework will provide:

The tool will allow:


The case studies will illustrate the use of the tools to accomplish the goals of the framework.
 

No./Title:             Pearce - 2     Integrating UML-Specified Information with HLA Simulations
Level:                  Master's
Background:       discrete event simulation

Synopsis: UML is being used to model a variety of information. This project is a first step in exploring the feasibility of integrating UML-specified information into an HLA simulation framework. The research involves:

No./Title:             Pearce - 3     HLA-Compliant Simulation & Surrogate for Hardware Subsystems
Level:                  Master's
Background:       embedded systems, discrete event simulation

Synopsis: In this research, the hardware of interest are specialized components (like I/O components or ASICs) that would reside as a subsystem on a general purpose target computer system. Developing software for these customized hardware sub-systems can be difficult:

Research is needed to develop an HLA-based simulation environment that will support both simulation and surrogate harnesses for hardware sub-systems. As a simulation harness, the environment will allow HLA-compatible models of hardware sub-systems to be exercised by HLA-compliant application software. As a surrogate harness, the environment will allow hardware prototypes to replace their HLA models for hardware-in-the-loop execution.
 
 

No./Title:             Pearce - 4         The Predictable Development of Real-Time Systems
Level:                  Master's
Background:       real-time systems, software engineering

Synopsis: In a hard real-time system, failure to meet a time-critical deadline has catastrophic results (for example, loss of life and/or property). The development of hard real-time systems must allow conclusions (predictions) to be drawn regarding the ability of a system to meet its time-critical deadlines. Research has been carried out in many related areas, including: programming languages, operating systems, scheduling, modeling (for analysis and simulation), and supporting hardware issues. Unfortunately, a reality-gap exists between the theoretical research results and the practical application of the results. Research is needed in this area with the goal of bridging the reality-gap by exploring the practical application of theoretical results. Ideally, tools can be proposed/built to simplify the application of theory in a practical and realistic environment.
 

No./Title:             Pearce - 5         A Virtual Machine Based Method for DSP Software Development
Level:                  Master's
Background:       DSP systems, software development

Synopsis: Digital Signal Processor (DSP) architectures perform certain data manipulation tasks very efficiently; however, the control flow aspects of the architectures differ from traditional Von Neumann-style architectures. As the architectures become more complex (e.g. parallel DSP processors in a single chip), DSP software must be developed at increasing levels of abstraction. The design and analysis of DSP applications are often well-suited to a data-flow abstraction, and existing tools allow proof-of-concept simulation based on data-flow models. Unfortunately, the automatic code generation tools that map the data-flow model onto the DSP target-platform are designed to be general, and the tools do not account for some of the unique control flow aspects of DSP architectures. As a result, the generated code is often inefficient. Masters-level research is needed in this area with the goal of proposing a DSP software development method based on a data-flow abstraction. The research would include the implementation of a prototype data-flow virtual machine that would simplify, and improve the efficiency of, the development of DSP target-platform software.
 

No./Title:              Pearce - 6         Compilation for Embedded Systems
Level:                   Master's, Ph.D.
Background:         embedded systems

Synopsis: The development of embedded system software requires knowledge of the hardware platform on which the embedded application will execute. Compilers are designed for portability, and do not often have integrated knowledge of specific platform features. Research is needed to

No./Title:               Pearce - 7     Faster Simulation Through Steady State Abstractions
Level:                    Master's, Ph.D.
Background:         simulation, computer system architecture

Synopsis: The modeling of a computer system may involve the integration of multiple hardware components. In some cases, the components may have state-based behaviour models constructed in a hardware-oriented language (such as Verilog). Simulation of a system in terms of low-level hardware descriptions typically involves fine-grained state transitions. These transitions may be essential to describe some behaviour scenarios, however, the overhead of the low-level details may slow the simulation unnecessarily in scenarios where the details are not needed. A course-grained (more abstract) model describes behaviour in higher-level transitions. Simulation speed can often be improved by using a course-grained model instead of a fine-grained model. Research is needed to develop course-grained modeling techniques that can be applied together with fine-grained models to allow simulations to optimize performance by using the appropriate model in appropriate scenarios.
 

No./Title:              Pearce - 8     High Availability in a Distributed System
Level:                   Master's
Background:         real-time systems

Synopsis: The scale of real-time embedded systems has been steadily increasing, and it is common to find embedded networks that are dedicated to a particular applications. For example, vehicles like aircraft and autonomous robots are often equipped with their own internal networks.

Much research has been done on the middleware to support high availability of these real-time distributed systems (for example: HADES). The middleware presents a fault-tolerant virtual platform for the execution of distributed applications. The theoretical analysis, practicality and overhead penalties in using such middleware are still open research areas.

The proposed research will involve porting HADES (or re-implementing a subset) in a distributed POSIX-o/s environment into which faults can be injected (the Carleton RADS Lab has such a distributed test facility; it is currently configured as a Linux environment). The work will include:


The research might change slightly to focus on a robotics environment, but this depends on a joint research grant proposal that will not be confirmed until April, 2002.
 

No./Title:           Pearce - 9     Programming Education and Visualization Tools
Level:               Master's
Background:     programming, software engineering

Synopsis: Program development and visualization tools are often targeted at professional users who are knowledgeable and experienced software developers. Educational users often struggle with professional-calibre tools because these users have not yet acquired the breadth of knowledge and depth of experience necessary to use the tools effectively. Master's-level research is needed in this area with the following goals:

  • a survey of existing development and visualization tools (both professional and educational)
  • an analysis of educational user needs
  • a list of requirements for tools to address the educational user needs
  • a prototype that implements a subset of the requirements
  • Some preliminary work has been done on a high-level language teaching/simulation tool.
     



    last modified:    September 6, 2001