Welcome to the XPERTS @ SCE Homepage!
XPERTS@SCE is a collection of projects that entail aspects of embedded
(and/or) real-time systems. XPERTS@SCE can accommodate any project that can
be linked to the embedded real-time system theme. The goal is to accumulate
a set of ongoing team projects that have varying levels of interaction. Tightly
coupled projects may collaborate closely while developing project deliverables.
Loosely coupled projects may share technologies and expertise. Decoupled
projects might only share the common underlying theme of embedded real-time
systems. Some of next year's projects will build on the work of previous
projects, but XPERTS@SCE also encourages new projects that capitalize on
emerging technology and/or unique opportunities.
Ideally, project teams will consist of 3 to 5 of students. A moderated XPERTS@SCE
discussion group has been set up on Connect Groups to provide a meeting place
for students interested in projects, and to help students share ideas about
potential projects. To access the discussion group, you will need a Connect
Account (accounts are available to all Carleton students, see here for Connect
info).
The information and links provided below include:
information about the XPERTS@SCE concept,
details on how projects are managed under the XPERTS@SCE umbrella,
more project details,
late-breaking new project descriptions, and
links to related technical information.
The following are examples of some past projects: Some projects have taken
a systems focus involving hardware and software, for example: a microprocessor-based
performance trainer for a wheelchair athlete, simulation of a DSP-based voice
over IP telephone, and control of a human-in-the-loop motion simulation platform.
Software tools have also been popular, and past projects have developed a
range of tools for: visualizing programming using a state-based reactive paradigm,
supporting symbolic debugging, and manipulating and visualizing XML-based
representations of timing diagrams.
Several directions are proposed below for XPERTS@SCE
projects. The suggestions range from very specific projects, to general guidelines
towards potential project areas. Students with project ideas that are not
listed but fit the XPERTS@SCE theme are encouraged to discuss their ideas
with Prof.
Pearce.
The Real-Time Java Specification (RTJS) extends Java to include subclasses that support real-time programming. The "traditional" Java virtual machine is not compatible with the RTJS extensions, and a new virtual machine implementation is needed. This project will construct a Real-Time Java virtual machine targetted for embedded systems use. The goal will be a small footprint, and (ideally) compatibility with J2ME. There are several directions this project could take, including the use of FPGAs to implement some of the virtual machine functionality.
CUSP (Carleton University Simulator Project) is an ongoing joint project with the Department of Mechanical and Aerospace Engineering, and is carried out in the framework of Aerospace 4th year projects. Current Status: The first year has seen some long term planning towards a 6-degree-of-freedom platform, and the construction of a single-degree-of-freedom demonstrator (SiDFreD). Future Goals: Some of the goals for the second year will include detailed testing and performance evaluation of SiDFreD, the design and implementation of an Eclipse-based workbench for constructing CUSP simulations, extension of the demonstrator with an additional degree of freedom, and developing a new demonstrator application.
The VoIP Lab includes VoIP telephones built by Mitel, and based on Analog Devices DSP processors. An ongoing project is building a simulation of the telephone. The simulation is being developed using the DEVS method, and the CD++ tool. Current Status: A simulation of a subset of the DSP processor's functionality has been developed. Future Goals: There are a large number of directions for this project, including: extending the simulation of the processor, simulating supporting hardware, porting some of the telephone software from the target to the simulator, and integrating the simulation into the High Level Architecture (HLA) for simulation interoperability.
The RTI is the RunTime Infrastructure for the High Level Architecture (HLA). The HLA is an IEEE standard for simulation interoperability and reuse. The standard specifies the RTI interface (API) but not the RTI implementation. The RTI is the distributed middleware that allows a network of simulations to interact (some internet game hosting architectures, such as BattleNet, are based on similar middleware packages). There are several RTI commercial products available, and at least one open source version developed at Georgia Institute of Technology. This project is porting the Georgia Tech version from C to Java, and has the potential for collaboration with the Georgia Tech team. Current Status: a subset of the Georgia Tech RTI has been ported to Java, and some of the Georgia Tech demonstration federates can be executed. Future Goals: The preliminary version needs to be expanded to include more robust functionality. Ideally, the RTI functionality can be configured selectively, to allow the RTI to be optimized for particular applications.
The Timing Diagram Tool is a workbench
for working with timing diagrams. The tool supports the Timing Diagram Markup Language
(TDML), which is an XML-variant for describing timing diagrams. Current
Status: The Timing Diagram Construction project has established a preliminary
framework for editing timing diagrams visually. The framework accepts and
stores timing diagrams using TDML files. Another project has developed a
tool that allows Verilog outputs of timing diagram information to be transformed
into TDML representations. Future Goals: There are many potential
directions for this project, including: the extension of the TDC editor framework,
the development of an Eclipse-based
workbench to integrate TDML-based tools, and a comparison tool that allows
TDML representations of waveforms to be compared with TDML representations
of waveform specifications.
The ACE lab (Aviation and Cognitive Engineering) is located in Carleton's Centre for Applied Cognitive Research, and carries out human factors research. Research experiments involve placing people in realistic simulators and measuring their performance during operational scenarios. The lab currently houses a Griffon helicopter cockpit simulator, and a 5-channel truck simulator. Constructing an experiment involves customizing a simulator for particular scenarios and measurement configurations. The development process requires the use of an array of tools. This project will develop a "workbench" for constructing experiments for (one or more of) the ACE lab simulators. The workbench will be based on IBM's open-source Eclipse platform, and will organize the various tools involved behind a goal-directed user interface. Ideally, the workbench will simplify the development of simulation experiments by providing an environment with automated support for coordinating, controlling and integrating all related tasks.
Technology has pushed the gaming envelope to a point where real-time, distributed, interactive games are feasible. These games are often organized as a simulation, where state changes progress in real-time simulation steps, and state changes are communicated among all players at the end of each step. This project will develop a real-time, distributed, interactive game based on the HLA (IEEE standard 1516 High Level Architecture for simulation interoperability).
Please Note: The application of engineering design and development methods is a goal that will be strictly enforced. This project will not tolerate reckless hacking! Resistance is futile.
Most development environments include a "HelloWorld" application that exposes introductory details in using the environment. When a new user wants to experiment with the environment, the HelloWorld application is often used as a simple, "known to work" starting point that is evolved and extended while developing a better understanding of the environment. A "HelloWorld" application exists for the HLA (IEEE standard 1516 High Level Architecture for simulation interoperability), but it is limited in its ability to fulfill these goals. This project will enhance the existing PoolSim application (developed by the 2002/2003 CUSP team) to better meet the general goals of a "HelloWorld" application for the HLA. PoolSim currently provides a real-time simulation of a ball rolling on a pool table. The project will involve: extending PoolSim's functionality, porting PoolSim to Linux, developing tutorial documentation, establishing an open source web presence for PoolSim, and submitting an article about the HLA and PoolSim to the IEEE Potentials magazine.
The Discrete Event System Specification (DEVS) is a
mature methodology for modelling and simulation. DEVS is well suited to modelling
the discrete, state-based nature of embedded real-time systems, and has
been used in the VoIP Telephone Simulator project (above). DEVS variants
are used worldwide, and an international effort (led by Prof. Wainer) is
attempting to standardize the way in which DEVS-based tools interoperate.
This project will contribute to the standardization effort by developing
a workbench for integrating DEVS-based tools. The workbench will be based
on IBM's Eclipse platform, and will
begin with support for the CD++
tool.
OK, so where did the name come from? PERTS is an acronym for Projects in Embedded Real-Time Systems, but PERTS sounds a bit like a shampoo. Some current project students claim that all cool projects have an "X" in the name . . . so XPERTS seems like a good choice. A quick search for "XPERTS" on Google revealed that many people agree! . . . so the name was extended to include the home department (also makes the name unique in a Google search!). Is there anything special about the name? Well . . . there could be . . . it's all up to us.
Last Modified: March 11, 2003